1. Field of Invention
The present invention relates to substrates for electro-optical devices such as a reflective liquid crystal panel substrate, and particularly relates to an electro-optical device substrate comprising a pixel region formed on an element region for selecting a pixel.
2. Description of Related Art
The present applicant disclosed configurations of a liquid crystal panel substrate, a liquid crystal panel and a projection display device in Japanese Patent Application No. 8-279388 filed on Oct. 22, 1996, as described below. The projection display device (liquid crystal projector) using a reflective liquid crystal panel as a light valve includes, as shown in FIG. 17, a light source 110 arranged along the system optical axis L0; a polarized light illumination unit 100 including an integrator lens 120 and a polarized light converter 130; a polarized light beam splitter 200 for reflecting the S-polarized light beam emitted from the polarized light illumination unit 100 by an S-polarized light reflecting face 201; a dichroic mirror 412 for separating the blue light component (B) from the light reflected by the S-polarized light reflecting face 201 of the polarized light beam splitter 200; a reflective liquid crystal light valve 300B for modulating the separated blue light component (B); a dichroic mirror 413 for separating by reflection the red light component (R) from the light beams after separation of the blue light by a dichroic mirror 412; a reflective liquid crystal light valve 300R for modulating the separated red light component (R); a reflective liquid crystal light valve 300G for modulating the residual green light component (G) passing through the dichroic mirror 413; a projection optical system 500 including a projection lens for projecting synthesized light onto a screen 600, in which the light components modulated in the three reflective liquid crystal light valves 300R, 300G and 300B are synthesized by the dichroic mirrors 413 and 412 and the polarized light beam splitter 200 in their reverse paths. Reflective liquid crystal panel 30 shown in FIG. 18 as a cross-sectional view are used as the reflective liquid crystal light valves 300R, 300G and 300B.
The reflective liquid crystal panel 30 includes a reflective liquid crystal panel substrate 31 fixed with an adhesive on a supporting substrate 32 composed of glass or ceramic; a glass substrate 35 which is provided with a counter electrode (common electrode) 33 composed of a transparent conductive (ITO) film, and which lies at the incident light side, and is opposed with a gap to the reflective liquid crystal panel substrate 31 enclosed by a frame composed of a sealing agent 36; and a known twisted nematic (TN) liquid crystal or a super homeotropic (SH) liquid crystal 37 in which liquid crystal molecules are vertically aligned in a no-applied voltage state, the liquid crystal being sealed in the space enclosed by the sealing agent 36 between the reflective liquid crystal panel substrate 31 and the glass substrate 35.
FIG. 19 is a plan view of an enlarged layout of a reflective liquid crystal panel substrate 31 used in the reflective liquid crystal panel 30. The reflective liquid crystal panel substrate 31 includes a rectangular pixel region (display region) 20 provided with pixel electrodes disposed in matrix 14 shown in FIG. 18; gate line driver circuits (Y drivers) 22R and 22L lying at the exteriors of the right and left sides of the pixel region 20 for scanning gate lines (scanning electrodes or line electrodes); a precharging/testing circuit 23 lying at the exteriors of the upper side of the pixel electrode 14 for data lines (signal electrodes or column electrodes); an image signal sampling circuit 24 lying at the exterior of the bottom side of the pixel electrodes 14 for supplying image signals to the data lines in response to the image data; a sealing region 27 with a frame shape lying at the exterior of the gate line drivers 22R and 22L, the precharging/testing circuit 23 and the image signal sampling circuit 24, for placing a sealing agent 36; a plurality of terminal pads 26 arranged along the bottom end and connected to a flexible tape wiring 39 with an anisotropic conductive film (ACF) 38 therebetween; a data line driver circuit (X driver) 21 lying between the terminal pad array 26 and the sealing region 27 for supplying image signals to data lines in response to the image data; and relay terminal pads (so-called silver points) 29R and 29L lying beside both ends of the data line driver circuit 21 for energizing the counter electrode 33 on the glass substrate 35.
The peripheral circuits (the gate line driver circuits 22R and 22L, the precharging/testing circuit 23 and the image signal sampling circuit 24) lying at the interior of the sealing region 27 have a shading film 25 (refer to FIG. 18) to shield from the incident light, which is the same as the pixel electrodes 14 of the topmost layer.
FIG. 20 is an enlarged partial plan view of the pixel region 20 of the reflective liquid crystal panel substrate 31, and FIG. 21 is a cross-sectional view taken along the line A-Axe2x80x2 of FIG. 20. In FIG. 21, numeral 1 represents a single-crystal silicon Pxe2x88x92 semiconductor substrate (an Nxe2x88x92 semiconductor substrate is also available) having a side of 20 mm. Numeral 2 represents a P-type well region formed on the top surface (main face) in the device-forming region (MOSFET etc.) of the semiconductor substrate 1, and numeral 3 represents a field oxide film (so-called LOCOS) which is formed for separating devices in the non-element-forming region of the semiconductor substrate 1. The p-type well region 2 shown in FIG. 21 is formed as a common well region for the pixel region 20 provided with a matrix of pixels having dimensions of, for example, 768xc3x971024, and it is separated from a P-type well region 2xe2x80x2 (refer to FIG. 22) for fabricating the devices of the peripheral circuits (the gate line driver circuits 22R and 22L, the precharging/testing circuit 23, the image signal sampling circuit 24 and the data line driver 21).
The field oxide film 3 is provided with two openings in the divided region of each pixel. A gate electrode 4a composed of polycrystalline silicon or a metal silicide is formed via a gate insulating film 4b in the center of one opening; an N+ source region 5a, and an N+ drain region 5b formed on the P-type well region 2 at the both sides of the gate electrode 4a form a N-channel MOSFET (insulated-gate field effect transistor) for pixel selection together with the gate electrode 4a. Gate electrodes 4a in a plurality of pixels arrayed in a line extend in the scanning line direction (the line direction of the pixels) to form gate lines 4.
A P-type capacitor electrode region 8, which is common to the line direction, is formed on the P-type well region 2 in the other opening; a capacitor electrode 9a composed of polycrystalline silicon or a metal silicide formed on the P-type capacitor electrode region 8 with an insulating film (dielectric film) 9b therebetween forms a retention capacitor C for retaining a signal selected by the MOSFET for pixel selection together with the P-type capacitor electrode region 8.
A first interlayer insulation film 6 is formed on the gate electrode 4a and the capacitor electrode 9a, and a first metal layer composed mainly of aluminum is formed on the insulating film 6.
The first metal layer includes a data line 7 (refer to FIG. 20) extending in the column direction, a source electrode wiring 7a, which protrudes from the data line 7 in a comb shape and is brought into conductive contact with a source region 5a through a contact hole 6a, and a relay wiring 10 which is brought into conductive contact with the drain region 5b through a contact hole 6b and with the capacitor electrode 9a through a contact hole 6c. 
A second interlayer insulation film 11 is formed on the first metal layer which forms the data line 7, the source electrode wiring 7a, and the relay wiring 10, and a second metal layer essentially consisted of aluminum is formed on the second interlayer insulation film 11. The second metal layer includes a shading film 12 to cover the entire pixel region 20. The second metal layer as the shading film 12 forms a wiring 12b (refer to FIG. 22) for connecting the devices in the peripheral circuits (the gate line driver circuits 22R and 22L, the precharging/testing circuit 23, the image signal sampling circuit 24 and the data line driver circuit 21) formed on the periphery of the pixel region 20.
A plug hole 12a is provided at a position of the shading film 12 corresponding to the relay wiring 10. A third interlayer insulation film 13 is formed on the shading film 12, and a rectangular pixel electrode 14 which substantially corresponds to one pixel is formed as a reflective electrode on the interlayer insulation film 13. A contact hole 16 is formed through the third and second interlayer insulation films 13 and 11 so that it is located inside the opening 12a. After the contact hole 16 is filled with a high-melting-point metal such as tungsten by a CVD process, the high-melting-point metal layer formed on the third interlayer insulation film 13 and the front face of the interlayer insulation film 13 are flattened to form a mirror surface by a chemomechanical polishing (CMP) process. Next, an aluminum layer is formed by a low temperature sputtering process and a rectangular pixel electrode 14 with a side of 15 xcexcm to 20 xcexcm is formed by a patterning process. The relay wiring 10 and the pixel electrode 14 are electrically connected by a pillar connecting plug (interlayer conductive section) 15. A passivating film 17 is formed on the entire pixel electrode 14.
Alternatively, the connecting plug 15 may be formed by planarizing the third interlayer insulation film 13 by a CMP process, providing a contact hole and burying a high-melting-point metal such as tungsten.
The planarization of the third interlayer insulation film 13 by the CMP process is essential for depositing a pixel electrode 14 with a mirror surface as a reflective electrode on each pixel. The process is also essential for the formation of a dielectric mirror film on the pixel electrode 14 with a protective film therebetween. The CMP process uses a slurry (polishing liquid) composed of components which simultaneously prompt chemical etching and mechanical polishing of a wafer before scribing.
In the pixel region 20, however, the MOSFET for pixel selection, the electrode wirings 7a and 10 of the retention capacitor C and the shading film 12 are formed as underlying layers. Also, as shown in FIG. 22, in the peripheral circuit region (the gate line driver circuits 22R and 22L, the precharging/testing circuit 23, the image signal sampling circuit 24 and the data line driver circuit 21), the electrode wirings 7a and the wiring 12b between the devices are formed as underlying layers. Further, in the region of the terminal pad 26, a lower layer film 26a composed of the first metal layer and an upper layer film 26b composed of the second metal layer are formed. As a result, immediately after the deposition of the third interlayer insulation film 13, the surface level 13a represented by a broken line in FIG. 22 rises up at the pixel region, the peripheral circuit region and the terminal pad region. When polishing the surface of the third interlayer insulation film 13 having such large unevenness by the CMP process, the finished level 13b after polishing represented by the solid line in FIG. 22 reflects the original surface level 13a represented by the broken line. According to intensive investigations by the present inventor, it is clarified that the surface planarization of the third interlayer insulation film 13 on the pixel region is particularly important in the liquid crystal panel substrate 31 subjected to such polishing treatment.
Japanese Unexamined Patent Publication No. 9-68718 discloses a technology for planarization of the third interlayer insulation film 13 on the pixel region 20, in which discrete dummy patterns of the metal layer for individual pixels are provided between the first metal layer, such as the relay wiring 10, and the second metal layer (shading layer) to raise the level in order to suppress the entire surface unevenness of the shading film 12. When the intermediate metal layer is formed only for raising the level for each pixel, an additional step for depositing an interlayer insulation film should be incorporated. When the surface unevenness of the interlayer insulation film is reduced before polishing, the initial polishing rate in the CMP treatment unintentionally decreases, and thus planarization of the interlayer insulation film 13 to form a mirror surface requires a long polishing time and a large amount of polishing liquid. The deposition of dummy patterns on individual pixels in the pixel region 20 therefore has a disadvantage in the production process, resulting in increased production costs.
FIG. 23 is a contour plot of film illustrating the thickness distribution of the third interlayer insulation film 13 after polishing of the liquid crystal panel substrate 31, in which the third interlayer insulation film 13 with a thickness of approximately 24,000 xc3x85 is formed and then subjected to the CMP treatment until the residual thickness of the third interlayer insulation film 13 reaches approximately 12,000 xc3x85 in the center of the pixel region 20. In FIG. 24, a graph depicted by marks x shows the residual thickness distribution of the left seal in the vertical direction taken along line a-axe2x80x2 of FIG. 23. In FIG. 25, a graph depicted by marks x shows the residual thickness distribution of the central pixel in the vertical direction taken along line b-bxe2x80x2 of FIG. 23. In FIG. 26, a graph depicted by marks x shows the residual thickness distribution of the upper seal in the transverse direction taken along line c-cxe2x80x2 of FIG. 23. In FIG. 27, a graph depicted by marks x shows the residual thickness distribution of the central pixel in the transverse direction taken along line d-dxe2x80x2 of FIG. 23. In FIG. 28, a graph depicted by marks x shows the residual thickness distribution of the lower sealing region in the transverse direction taken along line e-exe2x80x2 of FIG. 23.
As shown in FIGS. 23 to 28, the maximum difference in the thickness is approximately 6,120 xc3x85 in the pixel region 20 and the sealing region 27, hence the substrate including the pixel region 20 and sealing region 27 as a whole is not sufficiently flattened. The periphery of the terminal pad 26 and the upper and lower centers of the sealing regions 27 are excessively polished, whereas the right and left centers of the sealing region 27 are insufficiently polished.
As shown in FIG. 22, since the protruding terminal pads 26 in spot shape are discretely arranged as an array in the terminal pad region, the protruding sections 13c covered with the third interlayer insulation film 13 will be rapidly polished. The region of the terminal pad 26 therefore has a higher initial polishing rate than that of the pixel region 20. Accordingly, the region of the terminal pad 26 may be excessively polished to expose the underlying layer (upper layer film 26b) before the pixel region 20 is sufficiently flattened.
A means for compensating for the excessive polishing of the terminal pad 26 includes thick deposition of the third interlayer insulation film 13. According to this method, even if the region of the terminal pad 26 is rapidly polished, planarization of the third interlayer insulation film 13 is almost completed in this region before the underlying layer is exposed, hence the polishing rate significantly decreases compared with the initial polishing rate. As a result, the pixel region 20 can be flattened by spending an increased polishing time without exposing the underlying layer.
The formation of the thick third interlayer insulation film 13 causes an increased depth of the contact hole for the connecting plug 15, and it is difficult to embed the contact hole 16 with the high-melting-point metal which constitutes the connecting plug 15 as a result of such a high aspect ratio. The contact hole 16 originally has a large depth because the connecting plug 15 is a conductive section skipping an interlayer, which is formed through the second interlayer insulation film 11, the shading layer 12 and the third interlayer insulation film 13, and reaches the pixel electrode 14. Further, the opening 12a and thus the diameter of the contact hole 16 must be reduced in order to prevent leakage of the light entering from the gap between the pixel electrodes 14 to the devices such as MOSFET and the like through the opening 12a. The contact hole 16 inevitably has a high aspect ratio. Thinning of the interlayer insulation film 13 to be polished is therefore required. As described above, however, the CMP process excessively polishes the third interlayer insulation film 13 in the region of the terminal pad 26.
Since the thickness of the upper and lower centers of the sealing region 27 is smaller than that of the pixel region because of excessive polishing in the region of the terminal pad 26, the upper and lower edges of the pixel region 20 and the upper and lower center of the sealing region 27 are excessively polished, as shown in FIG. 26 and 28. The four corners of the sealing region 27 at the right and left sides will have also small thicknesses because of the excessive polishing of the region of the terminal pad 26, whereas the right and left centers of the sealing region 27 are hardly polished because of a low initial polishing rate caused by the flatness of the sealing region 27 before polishing. As a result, the right and left sides of the sealing region 27 and the right and left edges of the pixel region 20 are insufficiently polished in their central portions. When the peripheral edges of the pixel region 20 and the sealing region 27 have such tilted faces, the reflectance of the pixel electrode 14 formed on the third interlayer insulation film 13 after polishing decreases, the cell gap is adjusted with difficulty in the liquid crystal assembly, and the sealing agent has unsatisfactory adhesiveness. When the contact hole 16 for the connecting plug 15 is provided after the CMP treatment, it is difficult to optimize the etching time for the contact hole because of the uneven thickness.
In view of the incompatible problems regarding the interlayer insulation film formed between the shading film and the pixel electrode and requiring the polishing treatment in the reflective liquid crystal panel substrate, a first object of the present invention is to provide an electro-optical device substrate, such as a liquid crystal panel substrate, comprising a layered film structure of a plurality of interlayer insulation films and a plurality of conductive layers alternately formed in a pixel region formed on a substrate, wherein the electro-optical substrate has a structure requiring no additional deposition step and having a uniform polishing rate for the interlayer insulation film without thickening of the interlayer insulation film.
A second object of the present invention is to provide an electro-optical device substrate, such as a liquid crystal panel substrate, which has a flattened polished surface of the interlayer insulation film in the sealing region as well as in the pixel region, an improved reflectance of the pixel electrode, and which permits ready adjustment of the cell gap, improved adhesiveness of the sealing agent, and an optimized etching time of the contact hole.
In a first means in the present invention for achieving the first object, in order to flatten the surface level of the unpolished interlayer insulation film as uniformly as possible, a dummy pattern for raising the level of an interlayer insulation film to be polished is formed on the entire exterior of the pixel region by using the previously formed wiring layer, instead of on the space in the pixel region. That is, the present invention is characterized by an electro-optical device substrate comprising a layered film structure of a plurality of interlayer insulation films and a plurality of conductive layers alternately formed in a pixel region, in which a switching element is arranged on the substrate in response to each pixel, at least one interlayer insulation film below the top conductive layer among the plurality of conductive layers being flattened by polishing; the substrate being characterized in that a dummy pattern with a single or a plurality of layers comprising the conductive layers below said interlayer insulation film subjected to the polishing is provided near at least a terminal pad formed at a non-pixel region on the substrate. The terminal pad includes an input terminal pad arranged near the edge of the substrate and a relay terminal pad provided at the inner position of the substrate.
Since the surface level of the formed interlayer insulation film to be polished is raised near the terminal pad in such a configuration of the dummy pattern provided near the terminal pad, the surface level is substantially the same as the surface level of the interlayer insulation film to be polished in the pixel region, and thus the surface level is made uniform over the entire surface. The uniform surface has a uniform polishing rate in chemomechanical polishing (CMP) or the like without prompted polishing near and outside the terminal pad region and the polished surface of the interlayer insulation film is more flattened than conventional surfaces. As a result, the pixel region is more satisfactorily flattened, control of the cell gap is improved in cell assembly using a counter substrate, and the etching time for the contact holes of the interlayer conductive portion etc., in the pixel region after polishing is easily determined.
Such a uniform polished surface prevents exposition of the underlying terminal pad layer due to excessive polishing at the terminal pad portion, and can achieve thinning of the unpolished interlayer insulation film. Since the aspect ratio of the contact hole at the interlayer conductive portion in the pixel electrode is improved by the thinning, an opening portion with a small diameter is achieved by a contact hole with a small diameter. As a result, shading characteristics are improved.
The interlayer conductive portion electrically connects the first conductive layer connecting to the switching element and the upper conductive layer formed on the interlayer insulation film to be polished, and the dummy pattern may be any one of a first dummy pattern composed of the first conductive layer, a second dummy pattern composed of the second conductive layer which is formed between the first conductive layer and the upper conductive layer such as the shielding film, and a composite thereof.
When a conductive dummy pattern lies near the terminal pads outside the pixel region, the dummy pattern functions as a shading film, hence it prevents the invasion of stray light from the exterior of the pixel region into the pixel region on the substrate, resulting in a suppressed photocurrent flow and an improved switching element.
Since the input terminal pad is connected to the external wiring by thermocompression bonding using an anisotropic conductive film, conductive particles damage the thinned interlayer insulation film after polishing over the dummy pattern region, and short-circuiting to the input terminal pad will occur. When a dummy pattern is formed over the almost entire range other than the external wiring region near the input terminal pads, two adjacent input terminal pads will cause short-circuiting through the dummy pattern.
In the present invention, the dummy pattern arranged on the periphery of the input terminal pads is composed of a plurality of divisional dummy patterns, hence the surface level of the formed interlayer insulation film to be polished is made uniform without short-circuiting between the adjacent terminal pads. The probability of the short-circuiting decreases as the number of divisional dummy patterns increases.
It is preferable that a non-dummy pattern region be provided between two adjacent input terminal pads. The non-dummy pattern region adjoins the wire of the flexible tape wiring which is compressed during the thermocompression bonding. If the dummy patterns are continuously formed, conductive particles in the anisotropic conductive film will raise the probability of short-circuiting between a terminal pad and dummy pattern, causing short-circuiting between two terminal pads through the dummy pattern. The formation of the non-dummy pattern can securely prevent such undesirable short-circuiting.
The distance between the input terminal pad and the divisional dummy pattern on its periphery is set to be larger than the distance between the wiring and the dummy pattern near the wiring in order to prevent as much as possible bridging and thus short-circuiting between the input terminal pad and the divisional dummy pattern through the conductive particles in the anisotropic conductive film.
The distance between the relay terminal pad and the dummy pattern on its periphery is set to be larger than the distance between the wiring and the dummy pattern near the wiring. Generally silver paste causes conduction on the relay terminal pad. Silver paste on the relay terminal pad will not cause short-circuiting to the dummy pattern near the relay terminal pad even if the silver paste slightly spreads out of the relay terminal pad.
In order to achieve the second object, a second means of the present invention is characterized in that dummy patterns composed of a single or plural conductive layers lying under the interlayer insulation film to be polished are provided on the sealing region surrounding the pixel region as well as near the terminal pad. When no dummy pattern is provided in the sealing region, the interlayer insulation film tends to have a slanted surface at the periphery of the pixel region before polishing. Such a slanted surface causes a low reflectance of the shading film of the upper conductive layer and a difficulty in optimization of the etching time for the formation of the hole due to an uneven thickness of the interlayer insulation film after polishing. The provision of the dummy pattern can solve such problems. The surface level of the unpolished interlayer insulation film is substantially uniform over the entire region, including the sealing region, near the pixel region, hence the polished interlayer insulation film barely has a slanted surface and an uneven thickness in the pixel region.
If no dummy pattern is provided at the exterior of the sealing region provided with a dummy pattern, the interlayer insulation film on the sealing region has a slanted surface after polishing. The slanted surface will disturb the control of the gap between two substrates (referred to as a cell gap) when adhering to the counter substrate in fabrication of an electro-optical device and cause a drawback to adhesiveness of the sealing agent.
It is preferable that a dummy pattern be provided at the peripheral region of the sealing region in order to solve these problems.
The dummy pattern may be the first dummy pattern composed of the first conductive layer electrically connected to the switching element, the second dummy pattern composed of the second conductive layer lying between the first conductive layer and the upper conductive layer such as the shading film, or a composite dummy pattern of the first and second dummy patterns.
Preferably, the dummy pattern provided at the sealing region and the peripheral region of the sealing region is formed on an isolated pattern which is the same layer as the control wiring layer of the switching element. Also, if required, the dummy pattern near the terminal pad region is preferably formed on an isolated pattern which is the same layer as the control wiring layer of the switching element. By using the pattern as a base plate for raising the bottom, planarization of the surface level of the polished interlayer insulation film can be more precisely controlled.
Further, the present invention is characterized in that a single or plural dummy patterns composed of conductive layer underlying the interlayer insulation film to be polished are provided at the neighboring region of the driver circuit which is provided at the periphery of the pixel region and supplies signals to the switching element. The provision of the dummy pattern at the medial region between the sealing region and the pixel region helps planarization of the interlayer insulation film by polishing. The dummy pattern may be the first dummy pattern composed of the first conductive layer, the second dummy pattern composed of the second conductive layer, or a composite dummy pattern of the first and second dummy patterns.
Further, the present invention is characterized in that a single or plural dummy patterns are provided at the corner region of the sealing region which is provided at the periphery of the pixel region, and the dummy patterns are composed of conductive layer underlying the interlayer insulation film to be polished and have a lower density than that of the periphery of a side region of the sealing region and the periphery of the corner region of the sealing region formed on the periphery of the pixel region. In the corner region of the sealing region, a plurality of divisional dummy patterns are distributed as groups, and the dummy patterns are different from wide continuous dummy patterns at the sealing side and on the periphery of the corner region. The surface roughness of the unpolished interlayer insulation film at the four-corner sealing portion is therefore reflected by the unevenness due to the divisional dummy patterns, and the four-corner portion has a higher initial polishing rate compared to the four-corner portion having a continuous wide dummy pattern. As a result, the polishing rate at the four-corner portion is equalized to that in the sealing region, and a change in residual thickness can be reduced in the pixel region and the sealing region.
The corner portion is indented and the boundary portion is cornered in the sealing region formed on the periphery of the pixel region, even when a single or plural dummy patterns composed of conductive layer underlying the interlayer insulation film to be polished are formed at the sealing region excluding the corner region, that is, even when no dummy pattern is formed at the four-corner portion. The boundary portion is therefore easily polished at the initial stage and a slanted surface is formed. The slanted surface gradually extends to the inner pixel region and the sealing region. Accordingly, the pixel region and the sealing region can be flattened or planarized as a whole.
Such dummy patterns may be the first dummy pattern composed of the first conductive layer, the second dummy pattern composed of the second conductive layer, or a composite dummy pattern of the first and second dummy patterns.
Also, the present invention is characterized in that a plurality of uneven pseudo pixel patterns including the conductive layer lying under the interlayer insulation film to be polished are formed at the non-pixel region on the substrate instead of the forming a continuous wide dummy pattern in the non-pixel region. In the substrate having uneven pseudo dummy patterns, since the unpolished interlayer insulation film at the non-pixel region and the pixel region have very similar uneven surface patterns, the initial polishing rate is almost equalized over the entire substrate and a highly precise surface flatness can be achieved at least in the pixel and sealing regions.
It is preferable that a plurality of uneven pseudo pixel patterns are formed repeatedly in the direction of two dimensions on the substrate such that the arrangement has spatial regularity. The regularity corresponds to the spatial regularity of the uneven pixel pattern such as matrix in the pixel region. The surface over the pixel region and the sealing region is further significantly flattened or planarized.
The uneven pseudo pixel pattern may be the first dummy pattern composed of the first conductive layer, the second dummy pattern composed of the second conductive layer, or a composite dummy pattern of the first and second dummy patterns. A pseudo pixel pattern including the pattern of the interlayer insulation film will more closely imitate the pixel pattern.
Preferably, the uneven pseudo pixel pattern is formed of at least a pseudo gate line and a pseudo data line. These form typical unevenness in the pixel and are concerned with regularity of unevenness in the pixel region.
An electro-optical device is fabricated using the electro-optical device substrate, and is suitable for use in display portions of various electronic devices, for example, a light valve of a projection display device.